1. Field of the Invention
This invention relates to an improved composition of slurries and a process for the chemical mechanical polishing or planarization of semiconductor wafers. More specifically, it relates to compositions of slurries containing sulfur-bearing compounds capable of converting copper to copper sulfide that are employed in the polishing of silicon wafers used to produce semiconductor chips.
2. Discussion of the Prior Art
During integrated circuit manufacture, semiconductor wafers used in semiconductor fabrication typically undergo numerous processing steps, including deposition, patterning, and etching steps.
Details of these manufacturing steps for semiconductor wafers are reported by Tonshoff et al., “Abrasive Machining of Silicon”, published in the Annals of the International Institution for Production Engineering Research, (Volume 39/2/1990), pp. 621-635. In each manufacturing step, it is often necessary or desirable to modify or refine an exposed surface of the wafer in order to prepare the wafer for subsequent fabrication or manufacturing steps.
In conventional semiconductor device fabrication schemes, a silicon wafer is subjected to a numerous processing steps that deposit uniform layers of two or more discrete materials which together form a single layer of what will become a multi-layer structure. In this process, it is common to apply a uniform layer of a first material to the wafer itself or to an existing layer of an intermediate construct by any of the means commonly employed in the art, to etch pits into or through that layer, and then to fill the pits with a second material. Alternatively, features of approximately uniform thickness comprising a first material may be deposited onto the wafer, or onto a previously fabricated layer of the wafer, usually through a mask, and then the regions adjacent to those features may be filled with a second material to complete the layer. Following the deposition step, the deposited material or layer on a wafer surface generally needs further processing before additional deposition or subsequent processing occurs. When completed, the outer surface is substantially globally planar and parallel to the base silicon wafer surface. A specific example of such a process is the metal Damascene processes.
In the Damascene process, a pattern is etched into an oxide dielectric (e.g., SiO2) layer. After etching, optional adhesion and or barrier layers are deposited over the oxide surface. Typical barrier layers may include tantalum, tantalum nitride, titanium nitride or titanium, or tungsten. Next, a metal (e.g., copper) is deposited over or on top of the adhesion and or barrier layers. The copper metal layer is then modified, refined or finished by removing the copper metal and regions of the adhesion and or barrier layer on the surface of the underlying dielectric. Typically, enough surface metal is removed so that the outer exposed surface of the wafer comprises both metal and an oxide dielectric material. A top view of the exposed wafer surface would reveal a planar surface with copper metal corresponding to the etched pattern and dielectric material adjacent to the copper metal. The copper (or other metal) and oxide dielectric material(s) located on the modified surface of the wafer inherently have different hardness values and susceptibly to controlled corrosion. The method to modify the surface of the semiconductor may be a combination of a physical and chemical process. Such a process is called chemical mechanical planarization (CMP). An abrasive CMP process used to modify a wafer produced by the Damascene process must be engineered to simultaneously modify the metal (e.g., copper) and dielectric materials without scratching the surface of either material. The abrasive process must create a planar outer exposed surface on a wafer having an exposed area of a metal and an exposed area of a dielectric material.
Chemical mechanical polishing (or planarization) (CMP) is an area in semiconductor processing undergoing rapid changes. CMP provides global (millimeter-sized dimensions) and local (micron to nanoscale-sized) planarization on the wafer surface. This planarity improves the coverage of the wafer with dielectric materials and metals (e.g., copper) and increases lithography, etching and deposition process latitudes. Various equipment companies are advancing CMP technology through improvements in the engineering aspects of CMP while chemical companies are focusing on consumables such as slurries and polishing pads. For example, conventional CMP methods for modifying or refining exposed surfaces of structured wafers uses techniques that polish a wafer surface with a slurry containing a plurality of loose abrasive particles dispersed in an aqueous medium. Typically this slurry is applied to a polishing pad and the wafer surface is then ground or moved against the pad in order to remove the desired material from the wafer surface. Generally, the slurry may also contain chemical agents that react with the wafer surface.
A relatively new alternative to CMP slurry methods uses an abrasive pad to planarize a semiconductor surface and thereby eliminate the need for the foregoing slurries containing polishing particles.
This alternative CMP process is reported in International Publication No. WO 97/11484, published Mar. 27, 1997. The abrasive pad has a textured abrasive surface that includes abrasive particles dispersed in a binder. During polishing, the abrasive pad is contacted with a semiconductor wafer surface, often in the presence of a working slurry containing no additional abrasive particles, with a motion adapted to modify a single layer of material on the wafer and thus provides a planar, uniform wafer surface. The working slurry is applied to the surface of the wafer to chemically modify or otherwise facilitate the removal of a material from the surface of the wafer under the action of the abrasive article.
Working slurries of the prior art useful in the process described above, either in conjunction with the aforementioned slurries or the abrasive pad, are typically aqueous slurries of a variety of additives including complexing agents, oxidizing agents, passivating agents, surfactants, wetting agents, buffers, viscosity modifiers or combinations of these additives. Additives may also Include agents that are reactive with the second material, e.g., metal or metal alloy conductors on the wafer surface such as oxidizing, reducing, passivating, or complexing agents. Examples of such working slurries may be found, for example, in U.S. patent application Ser. No. 09/091,932 filed Jun. 24, 1998.
Variables that may affect wafer CMP processing include the selection of the appropriate contact pressure between the wafer surface and abrasive article, type of slurry medium, relative speed and relative motion between the wafer surface and the abrasive article, and the flow rate of the slurry medium. These variables are interdependent, and are selected based upon the individual wafer surface being processed.
CMP processes for modifying the deposited metal layer until the barrier layer or oxide dielectric material is exposed on the wafer outer surface leaves little margin for error because of the sub-micron dimensions of the metal features found on the wafer surface. The removal rate of the deposited metal should be relatively fast to minimize the need for additional expensive CMP tools, and the metal must be completely removed from the areas that were not etched. The metal remaining in the etched areas must be limited to discrete areas while being continuous within those areas or zones to ensure proper conductivity. In short, the metal modification process must be uniform, controlled, and reproducible on a sub-micron to nano-scale dimension.
In the CMP processes mentioned above, dishing performance, scratches or defects and removal rate of the metal are measurements of CMP performance. These performance measurements may depend on the use of the foregoing working slurries. Dishing is a measure of how much metal, such as copper, is removed from bond pads or wire traces below the plane of the intermediate wafer surface as defined by the difference in height between the copper and the tops of the barrier or dielectric layers following removal of the blanket copper or copper plus barrier layer. Removal rate refers to the amount of material removed per unit time. Removal rates greater than at least about 1000 A per minute are preferred. Lower removal rates, such as a few hundred angstroms per minute (A/min) or less, are less desirable because they tend to create increases in the overall manufacturing costs (cost of ownership) associated with wafer manufacture.
To minimize dishing and increase removal rates of layered surface materials on semiconductor devices, it is important to engineer slurries with components in narrow concentration ranges and pH values. The pH of the slurries used in polishing of semiconductor devices is dependent upon the composition of the surface layer to be polished. In most cases, it is necessary to engineer a slurry with a proper pH to effectively produce an oxide layered surface at the same rate the mechanical action of abrasion removes this layered oxide. For copper polishing slurries, U.S. Pat. No. 6,117,783 shows the importance of pH of about 6.0 to form a copper(I) oxide, Cu2O. Cuprous oxide can form only in near-neutral to slightly basic media. In low pH slurries, a protective oxide may not form on the copper surface thus increasing the propensity for aggressive attack by the oxidizing agent on copper metal. In high pH slurries, removed copper may precipitate from solution resulting in un-wanted particulate matter adhering to the wafer surface. Therefore, copper-polishing slurries must be formulated within a narrow pH window to ensure a high yield after CMP.
Prior art related to CMP includes the following:
U.S. Pat. No. 4,233,112 (Dart Industries) in which Valayil and Elias disclose the use of polysulfides as catalysts for hydrogen peroxide, useful in accelerating the dissolution of copper from circuit boards. This early disclosure allowed extrapolation to removal of copper from wafers, the basis of much of the prior art.
Removal rate acceleration by sulfur compounds has been a major focus of many patent filings. In WO01/44396 (Rodel Holdings), Sachen et. al. described slurries containing mercaptans, disulfides and glycolates, which demonstrated accelerated copper removal rates. In WO01/12740 (Cabot Microelectronics), Wang et.al. also described organosulfur compounds as removal rate enhancing. In WO01/12741 (Cabot), Wang et.al. again described organosulfur corrosion accelerants in compositions also containing corrosion “stoppers”.
U.S. Pat. No. 6,117,795 (LSI Logic), in which organosulfur compounds are discussed by Pasch as corrosion inhibitors for metal removal compositions. In U.S. Pat. No. 6,068,879, Pasch disclosed the utility of similar compounds in post-etch cleaners.
U.S. Pat. No. 5,073,577 (Morton International) in which Anderson discusses stable emulsions of high molecular weight polysulfides, which can be cured to produce sealants.
In Production of Sulfide Minerals by Sulfate-Reducing Bacteria During Microbiologically Influenced Corrosion of Copper, McNeil, Jones, and Uttle show that non-adherent layers of chalcocite (Cu2S) are formed on copper surfaces under some conditions. A Pourbaix diagram is published which details conditions under which copper sulfides and oxides are stable.
It would be desirable to provide improvements in chemical mechanical planarization by providing working slurries useful in modifying exposed intermediate copper surfaces of structured wafers for semiconductor fabrication and to methods of modifying the exposed copper intermediate surfaces of such wafers for semiconductor fabrication, preferably with improved, sustainable, copper removal rates and utilizing the foregoing family of working slurries. It would be especially desirable to provide working slurries that are more stable than commercially available slurries. It would also be desirable to provide working slurries that are useful in the aforementioned methods and resulting in the fabrication of copper containing structured wafers with better planarity and less defects.